• AD9958BCPZ
  • AD9958BCPZ
  • AD9958BCPZ
  • AD9958BCPZ
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The AD9958 consists of two DDS cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout related mismatches. Because both channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9958 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9958 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation. The AD9958 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPIcompatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0 / SDIO_1 / SDIO_2 / SDIO_3) that allow four programmable modes of serial I/O operation. The AD9958 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates two integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier. The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. The DDS acts as a high resolution frequency divider with the REFCLK as the input and the DAC providing the output. The REFCLK input source is common to both channels and can be driven directly or used in combination with an integrated REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REFCLK multiplier. The AD9958 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires the pin labeled DVDD_I/O (Pin 49) be connected to 3.3 V. The AD9958 operates over the industrial temperature range of −40°C to +85°C. Applications Agile local oscillators Phased array radars/sonars Instrumentation Synchronized clocking RF source for AOTF Single-side band suppressed carriers Quadrature communications

No. of Inputs-
Clock Frequency-
Supply Voltage Min1.8V
Supply Voltage Max3.3V
Logic Case Style-
No. of Pins56Pins
Operating Temperature Min-40°C
Operating Temperature Max85°C
PackagingEach
Product RangeAD9958 Series
RoHS Phthalates CompliantYes
MSLMSL 3 - 168 hours
SVHCNo SVHC (07-Jul-2017)
IC Case StyleCSP
Termination TypeSurface Mount Device
Количество в упаковке1
КорпусLFCSP-56
Вес0.06 г
supply_voltage_dc1.71 V (min)
rohs_statusCompliant
number_of_channels4
reach_svhc_complianceNo SVHC
lead_free_statusContains Lead
mounting_styleSurface Mount
packagingTray, Bulk
frequency500 MHz
sample_rate500 MHz
supply_current105 mA
lifecycle_statusActive
number_of_bits10
pin_count56
resolution_bits10.0
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