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FPGA, ACEX 1K, 50K GATES, TQFP144; Programmable Logic Type:PLD; Logic IC Function:FPGA; Logic IC Base Number:EP1K50; No of I/O Lines:102; No. of Macrocells:2880; Frequency:180MHz; I/O Interface Standard:LVTTL, LVCMOS; Voltage, Supply Min:2.375V; Voltage, Supply Max:2.625V; Case Style:TQFP; Operating Temperature Range:0°C to +70°C; Base Number:1; IC Generic Number:1K50; No. of Gates:50000; No. of Pins:144; Supply Voltage:2.50V; Temp, Op. Max:70°C; Temp, Op. Min:0°C; Termination Type:SMD
| supply_voltage_dc | 2.50 V |
| number_of_gates | 50000 |
| number_of_i_o_pins | 102 |
| reach_svhc_compliance | No SVHC |
| lead_free_status | Lead Free |
| mounting_style | Surface Mount |
| packaging | Tray |
| case_package | TQFP |
| frequency | 180 MHz |
| ram_bytes | 5120 B |
| rohs_status | Compliant |
| pin_count | 144 |
| CPLD Type | - |
| No. of Macrocells | 2880 |
| No. of I/O's | 102I/O's |
| Logic Case Style | TQFP |
| No. of Pins | 144Pins |
| Frequency | 180MHz |
| Supply Voltage Min | 2.375V |
| Supply Voltage Max | 2.625V |
| Propagation Delay | - |
| Global Clock Setup Time | 500ps |
| Operating Temperature Min | 0°C |
| Operating Temperature Max | 70°C |
| Packaging | Each |
| Product Range | - |
| MSL | MSL 3 - 168 hours |
| SVHC | No SVHC (17-Dec-2015) |
| Base Number | 1 |
| Clock Management | PLL |
| Core Supply Voltage Range | 2.375V to 2.625V |
| FPGA Family | ACEX 1K |
| I/O Interface Standard | LVCMOS, LVTTL |
| I/O Supply Voltage | 3.6V |
| IC Generic Number | 1K50 |
| Logic IC Base Number | EP1K50 |
| Logic IC Function | FPGA |
| No. of Gates | 50000 |
| No. of Logic Blocks | 360 |
| No. of Speed Grades | 1 |
| Operating Temperature Range | 0°C to +70°C |
| Programmable Logic Type | PLD |
| Supply Voltage | 2.5V |
| Supply Voltage Range | 2.38V to 2.63V |
| Termination Type | Surface Mount Device |
| Total RAM Bits | 40960 |
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